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IP Protection Of Semiconductor Layout Designs Under Trips And Indian Law




Bharvi Shahi, Christ University, Bengaluru


ABSTRACT


The research talks about the protection of semiconductor integrated circuit layout designs or topographies are an essential component of intellectual property (IP) law as it relates to current technological developments. Because these designs embody the three-dimensional form of electronic circuits that serve as the basis for microchips and integrated circuits, they can have significant financial value over the cost of developing the subject design. However, they may also be particularly vulnerable to copying and unauthorized reproduction. International law, specifically the legal obligation of the international community under the Agreement on Trade- Related Aspects of Intellectual Property Rights (hereinafter "TRIPS"), was one of the first instruments to recognize the need for protection of layout designs/emplacement of integrated circuits. The sections of the TRIPS Agreement that relate to layout designs are Article 35 to Article 38 which obligate members, including the United States, to protect the layout designs of integrated circuits in accordance with the terms of the Washington Treaty of 1989, which has yet to enter into force. India implemented the Semiconductor Integrated Circuits Layout-Design Act, 2000 (SICLDA) in accordance with TRIPS obligations, starting in 2001, showing India's potential to pursue innovation and protections for semiconductor layout designers. This legislation provides sui generis protection, and considers layout design as a unique form, distinct from copyright and patent law. In accordance with the Act, a layout design is - "original" which is identified as having come from an intellectual effort, which is not common. To receive registration under the Act, an "original" layout design must not have been commercially exploited anywhere in the world prior to the application for registration. The right holder will be granted exclusive rights for a period of 10 years, once it is registered which includes the right to reproduce, license, and get commercially exploited. The Act imposes a significant penalty for infringement, which allows civil and criminal remedies making the Act more deterrent. Notwithstanding the formal legal framework of semiconductor IP protection in India, the research identifies and intend to fill a number of considerable research gaps. These include the absence of empirical evidence we have of the post-graduate student at School of Law at Christ (Deemed to be University) practical use and enforcement of the law in India, no judicial interpretation or case law, and the apparent lack of understanding of the the protection by industry. The research will also look to exploit the ambiguity and overlap with other IP rights, and the largely unexplored area of institutional infrastructure as an important role in the practical administration of the Act. The aim of the research is to fill these gaps and to provide a comprehensive assessment of the existing legal framework, whilst offering recommendations for practical enhancements to India's semiconductor IP ecosystem regarding India's aspirations for, and ambitions to develop its electronics manufacturing capacity and technological self-reliance.


Keywords: Semiconductors, IP protection, Infringement, registration, integrated circuits.



Indian Journal of Law and Legal Research

Abbreviation: IJLLR

ISSN: 2582-8878

Website: www.ijllr.com

Accessibility: Open Access

License: Creative Commons 4.0

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All research articles published in The Indian Journal of Law and Legal Research are fully open access. i.e. immediately freely available to read, download and share. Articles are published under the terms of a Creative Commons license which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

 

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The opinions expressed in this publication are those of the authors. They do not purport to reflect the opinions or views of the IJLLR or its members. The designations employed in this publication and the presentation of material therein do not imply the expression of any opinion whatsoever on the part of the IJLLR.

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